As successive layers of conductive and dielectric materials are deposited during fabrication of semiconductor devices, unevenness often develops in the surface topography of the layers, i.e., certain surface regions of a layer become elevated relative to other surface regions of the layer. As such, surface topographies generally need to be planarized for further processing. Chemical-mechanical (chem-mech) polishing is one method of planarizing such surfaces. During chem-mech polishing, the surface is brought into contact with a rotating polish pad in the presence of an abrasive slurry. A portion of the surface is then abrasively removed by the mechanical action of the polish pad and the chemical action of the slurry.
One difficulty encountered during chem-mech polishing is that polishing rates vary considerably for different materials and different regions. Thus, care must be observed to avoid overpolishing of an overlying layer so as to cause damage to an underlying layer.
Polish selectivity is a comparison of the removal rate of one material relative to that of another material. Polish selectivity is a mechanism often exploited to avoid unintentional polishing of a material. In this regard, a polish stop comprises material that is more resistant to the effects of chem-mech polishing in comparison to other material, i.e., the polish stop material is polish selective to the other material. The polish stop can thus be strategically positioned so as to indicate when the chem-mech polishing should be terminated so that damage to an underlying material due to overpolishing can be avoided.
As a specific example, in order to fabricate a gate for utilization in certain present day semiconductor devices, a gate stack is designed with a doped polysilicon conductor, a titanium silicide cap on the polysilicon conductor, and an insulating cap oxide on the titanium silicide cap. Reactive-ion-etching is implemented to define the shape of the gate; and spaces adjacent to the gate resulting from the reactive-ion-etching are filled with polysilicon. Although polysilicon is a conductor, and not an insulator, the spaces are filled with polysilicon in this manner in order to form a polysilicon mandrel. Use of polysilicon as a mandrel takes advantage of the chem-mech polish selectivity between polysilicon and oxide. In this regard, the chem-mech polish selectivity allows the polysilicon mandrel to be polished down to the oxide gate cap, such that a "hard" stop is realized at the oxide gate cap. A polysilicon cap extension is then deposited, contact holes are etched into the polysilicon, and the contact holes are filled with material appropriate for forming contact studs, such as tungsten. Planarization of the structure is then achieved by chem-mech polishing. The hard stop of chem-mech polishing of polysilicon on oxide allows for reduction in chem-mech polishing tolerances across the wafer so that the height of each of the contact studs can be made to be uniform. The polysilicon mandrel must then be removed after the tungsten studs are formed, and replaced with appropriate insulative material, such as Phosophorous-Silicate Glass (PSG) oxide. Unfortunately, the additional processing required to remove the polysilicon mandrel, refill with PSG oxide, and re-planarize is time-consuming, inefficient and costly.
Further, it is extremely difficult to completely remove all the polysilicon during the reactive-ion-etching step. More specifically, it has been found to be virtually impossible to remove all the polysilicon from the re-entrant slopes on the gates and regions under the tungsten studs. Incomplete removal of polysilicon frequently results in undesirable contact-to-contact shorting or leakage.
Thus, there remains a need for a polish stop which will allow for improved efficiency and cost-effectiveness during semiconductor manufacturing.